implementation-flow

implementation-flow is a thesis project benchmarking interoperability between open-source and proprietary IC design flows. The same RTL design is pushed through four EDA-tool / PDK combinations and compared on Power, Performance, and Area (PPA):

Flow	EDA tools	PDK
A	Yosys + OpenROAD + KLayout (open)	Open (Sky130)
B	Yosys + OpenROAD + KLayout (open)	Closed (e.g. TSMC/Intel 55 nm)
C	Design Compiler + Innovus + Calibre (closed)	Open (Sky130)
D	Design Compiler + Innovus + Calibre (closed)	Closed

Flows A/B run on any machine with the open toolchain installed. Flows C/D require lab-only licensed tools and are out of scope for these docs.

This site documents the Flow A pipeline (Yosys synthesis + OpenROAD place-and-route on the open Sky130 PDK) as a reusable flow: how to run it end-to-end on any SystemVerilog design and testbench, and what to change if you retarget it to a different PDK, such as a closed 55 nm node (Flow B).

Note

Status: RTL simulation through post-route SDF-back-annotated gate-level simulation is implemented and validated. GDSII generation, KLayout, DRC, and LVS are not yet implemented — see the status note at the top of Running Flow A on Your Own SV Design for details.

Contents

• Getting Started
  • 1. FuseSoC
  • 2. oss-cad-suite (Yosys, Icarus, Verilator, GTKWave, nextpnr, …)
  • 3. OpenROAD
  • 4. KLayout
  • 5. PDK (Sky130, via ciel)
  • 6. Bender (multi-file / multi-module designs)
  • 7. Verify the read_slang SystemVerilog frontend
  • Environment checklist
• Flow A: Overview
  • Pipeline stages
  • Why FuseSoC only covers two stages
  • Output layout
  • Why the flow works this way
• Running Flow A on Your Own SV Design
  • The core idea
  • Project layout
  • 1. Bender.yml — declare your sources
  • 2. scripts/yosys_common.tcl — the file you actually write
  • 3. FuseSoC core file — RTL simulation
  • 4. Synthesis
  • 5. Post-synthesis gate-level simulation
  • 6. Pre-route PPA
  • 7. constraints/<design_name>.sdc — clocked designs only
  • 8. Place & route
  • 9. Post-route SDF-back-annotated simulation
  • Real-activity power (optional, recommended)
  • Known gotchas
• PDK Portability (e.g. Retargeting to 55 nm)
  • What stays the same
  • What must change
  • Suggested workflow for a retarget
  • Closed/licensed PDKs specifically
• Troubleshooting
  • Environment / install
  • Synthesis
  • Gate-level simulation
  • Place & route
  • Multi-file designs (Bender / read_slang)
  • Documentation build

Quick links

• Getting the toolchain installed: Getting Started

• What the flow does and why it’s structured this way: Flow A: Overview

• Dropping in your own design/testbench and running RTL → GDS: Running Flow A on Your Own SV Design

• Retargeting the flow to a different PDK (e.g. a 55 nm node): PDK Portability (e.g. Retargeting to 55 nm)

• Known gotchas and their fixes: Troubleshooting