implementation-flow

implementation-flow is a thesis project benchmarking interoperability between open-source and proprietary IC design flows. The same RTL design is pushed through four EDA-tool / PDK combinations and compared on Power, Performance, and Area (PPA):

Flow

EDA tools

PDK

A

Yosys + OpenROAD + KLayout (open)

Open (Sky130)

B

Yosys + OpenROAD + KLayout (open)

Closed (e.g. TSMC/Intel 55 nm)

C

Design Compiler + Innovus + Calibre (closed)

Open (Sky130)

D

Design Compiler + Innovus + Calibre (closed)

Closed

Flows A/B run on any machine with the open toolchain installed. Flows C/D require lab-only licensed tools and are out of scope for these docs.

This site documents the Flow A pipeline (Yosys synthesis + OpenROAD place-and-route on the open Sky130 PDK) as a reusable flow: how to run it end-to-end on any SystemVerilog design and testbench, and what to change if you retarget it to a different PDK, such as a closed 55 nm node (Flow B).

Note

Status: RTL simulation through post-route SDF-back-annotated gate-level simulation, GDSII generation via KLayout, DRC, LVS, antenna checks and multi-corner timing are implemented and validated on the reference design, which closes setup and hold at the ss, tt and ff corners at 28 ns. Known limits (7 library-cell li.5 DRC findings, 7 residual antenna violations, RC corners that vary resistance only) are listed in Flow A: Signoff and Results.

Contents