====================
implementation-flow
====================

**implementation-flow** is a thesis project benchmarking interoperability
between open-source and proprietary IC design flows. The same RTL design is
pushed through four EDA-tool / PDK combinations and compared on Power,
Performance, and Area (PPA):

.. list-table::
   :header-rows: 1

   * - Flow
     - EDA tools
     - PDK
   * - A
     - Yosys + OpenROAD + KLayout (open)
     - Open (Sky130)
   * - B
     - Yosys + OpenROAD + KLayout (open)
     - Closed (e.g. TSMC/Intel 55 nm)
   * - C
     - Design Compiler + Innovus + Calibre (closed)
     - Open (Sky130)
   * - D
     - Design Compiler + Innovus + Calibre (closed)
     - Closed

Flows A/B run on any machine with the open toolchain installed. Flows C/D
require lab-only licensed tools and are out of scope for these docs.

This site documents the **Flow A pipeline** (Yosys synthesis + OpenROAD
place-and-route on the open Sky130 PDK) as a reusable flow: how to run it
end-to-end on **any** SystemVerilog design and testbench, and what to change
if you retarget it to a different PDK, such as a closed 55 nm node
(Flow B).

.. note::

   **Status:** RTL simulation through post-route SDF-back-annotated
   gate-level simulation is implemented and validated. GDSII generation,
   KLayout, DRC, and LVS are **not yet implemented** — see the status
   note at the top of :doc:`running-your-own-design` for details.

.. toctree::
   :maxdepth: 2
   :caption: Contents

   getting-started
   flow-a-overview
   running-your-own-design
   pdk-portability
   troubleshooting

Quick links
===========

* Getting the toolchain installed: :doc:`getting-started`
* What the flow does and why it's structured this way: :doc:`flow-a-overview`
* Dropping in your own design/testbench and running RTL → GDS: :doc:`running-your-own-design`
* Retargeting the flow to a different PDK (e.g. a 55 nm node): :doc:`pdk-portability`
* Known gotchas and their fixes: :doc:`troubleshooting`